Multiply & Accumulate Unit Using RNS Algorithm & Vedic Mathematics: A Review
نویسندگان
چکیده
High speed execution of arithmetic operations and high degree of precision in real time system are of major concern in any digital signal processing (DSP). Speed of DSP depends on speed of multiplier and algorithm used. In this paper we propose Residue Number System method for fast “carry free” floating point arithmetic operations. Floating Point RNS units have obvious advantages over traditional fixed point multiply & accumulate (MAC) units. Performance of multiplier is enhanced by VHDL implementation of Floating Point Multiplier using ancient Vedic mathematics. The Urdhva Tiryakbhyam sutra is applicable to all cases of multiplication. Any multi-bit multiplication can be reduced down to single bit multiplication and addition using this method. Using these formulas, the carry propagation from LSB to MSB is reduces due to one step generation of partial product. Thus enhanced speed of arithmetic operation is the key challenges in design of MAC using RNS algorithm & Vedic multiplier.
منابع مشابه
Design and Implementation of Multiplier Using Kcm and Vedic Mathematics by Using Reversible Adder
This work is devoted for the design and FPGA implementation of a 16bit Arithmetic module, which uses Vedic Mathematics algorithms. For arithmetic multiplication various Vedic multiplication techniques like Urdhva Tiryakbhyam Nikhilam and Anurupye has been thoroughly analyzed. Also Karatsuba algorithm for multiplication has been discussed. It has been found that Urdhva Tiryakbhyam Sutra is most ...
متن کامل32-bit Mac Unit Design Using Vedic Multiplier
This paper presents Multiply and Accumulate (MAC) unit design using Vedic Multiplier, which is based on Urdhva Tiryagbhyam Sutra. The paper emphasizes an efficient 32-bit MAC architecture along with 8-bit and 16-bit versions and results are presented in comparison with conventional architectures. The efficiency in terms of area and speed of proposed MAC unit architecture is observed through red...
متن کاملA Novel Approach of Vedic Mathematics Using Reversible Logic
This paper is devoted for the design and implementation of a 32bit Arithmetic module it is used for vedic Mathematics algorithms. We have various arithmetic multiplication techniques like Urdhva, Tiryakbhyam, Nikhilam, and Anurupye has been thoroughly analyzed. A 32 x 32 bit multiplier using Urdhava Tiryakbhyam, it has been designed and using this multiplier, a MAC unit has been designed. An Ar...
متن کاملArithmetic Unit Implementation Using Delay Optimized Vedic Multiplier with Bist Capability
The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes has resulted in the integration of a number of processor cores into one chip. Still the load on the processor is not less in generic system. This load is reduced by supplementing the main processor with Co-Processors, which are designed to work upon specific type of functions like n...
متن کاملضربکننده و ضربجمعکننده پیمانه 2n+1 برای پردازنده سیگنال دیجیتال
Nowadays, digital signal processors (DSPs) are appropriate choices for real-time image and video processing in embedded multimedia applications not only due to their superior signal processing performance, but also of the high levels of integration and very low-power consumption. Filtering which consists of multiple addition and multiplication operations, is one of the most fundamental operatio...
متن کامل